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UCT UCT D ROD TE P TE PRO E SOL STITU OB UB LE S CA3130 SSIB Sheet PO Data
CA5130, CA5130A
March 2000 File Number 1923.6
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15MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output
CA5130A and CA5130 are integrated circuit operational amplifiers that combine the advantage of both CMOS and bipolar transistors on a monolithic chip. They are designed and guaranteed to operate in microprocessors or logic systems that use +5V supplies. Gate protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very high input impedance, very low input current, and exceptional speed performance. The use of PMOS field effect transistors in the input stage results in common mode input voltage capability down to 0.5V below the negative supply terminal, an important attribute in single supply applications. A complementary symmetry MOS (CMOS) transistor-pair, capable of swinging the output voltage to within 10mV of either supply voltage terminal (at very high values of load impedance), is employed as the output circuit. The CA5130 Series circuits operate at supply voltages ranging from 4V to 16V, or 2V to 8V when using split supplies. They can be phase compensated with a single external capacitor, and have terminals for adjustment of offset voltage for applications requiring offset null capability. Terminal provisions are also made to permit strobing of the output stage. The CA5130A, CA5130 have guaranteed specifications for 5V operation over the full military temperature range of -55oC to 125oC.
Features
* MOSFET Input Stage - Very High Zl . . . . . . . . . . . . . 1.5T (1.5 x 1012) (Typ) - Very Low ll . . . . . . . . . . . . . 5pA (Typ) at 15V Operation 2pA (Typ) at 5V Operation * Ideal for Single Supply Applications * Common Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can Be Swung 0.5V Below Negative Supply Rail * CMOS Output Stage Permits Signal Swing to Either (or Both) Supply Rails * CA5130A, CA5130 Have Full Military Temperature Range Guaranteed Specifications for V+ = 5V * CA5130A, CA5130 Are Guaranteed to Operate Down to V+ = 4.5V for AOL * CA5130A, CA5130 Are Guaranteed to Operate at 7.5V CA3130A, CA3130 Specifications
Applications
* Ground Referenced Single Supply Amplifiers * Fast Sample-Hold Amplifiers * Long Duration Timers/Monostables * High Input lmpedance Comparators (Ideal Interface with Digital CMOS) * High lnput Impedance Wideband Amplifiers * Voltage Followers (e.g., Follower for Single-Supply D/A Converter) * Voltage Regulators (Permits Control of Output Voltage Down to 0V) * Peak Detectors
Pinout
CA5130 (PDIP) TOP VIEW
OFFSET NULL INV. INPUT NON-INV. INPUT V-
1 2 3 4 +
8 7 6 5
STROBE V+ OUTPUT OFFSET NULL
* Single Supply Full Wave Precision Rectifiers * Photo Diode Sensor Amplifiers * 5V Logic Systems * Microprocessor Interface
Part Number Information
PART NUMBER (BRAND) CA5130AE CA5130E TEMP. RANGE (oC) -55 to 125 -55 to 125 PACKAGE 8 Ld PDIP 8 Ld PDIP PKG. NO. E8.3 E8.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
CA5130, CA5130A
Absolute Maximum Ratings
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Short circuit may be applied to ground or to either supply. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, V+ = 5V, V- = 0V, Unless Otherwise Specified TEST CONDITIONS VO = 2.5V VO = 2.5V VO = 2.5V VCM = 0V to 1V VCM = 0V to 2.5V Input Common Mode Voltage Range Power Supply Rejection Ratio Large Signal Voltage Gain (Note 3) VICR+ VICRPSRR AOL + = 1V; - = 1V VO = 0.1V to 4.1V RL = VO = 0.1V to 3.6V RL = 10k Source Current Sink Current Output Voltage VOM+ VOMVOM+ VOMVOM+ VOMSupply Current ISUPPLY VO = 0V VO = 2.5V NOTE: 3. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10k. RL = 2k RL = 10k ISOURCE ISINK VOUT RL = 4.99 4.4 2.5 5 0 4.7 0 3.5 0 50 260 0.01 0.01 0.01 100 400 4.99 4.4 2.5 5 0 4.7 0 3.5 0 50 260 0.01 0.01 0.01 100 400 V V V V V V A A VO = 0V VO = 5V CA5130 MIN 70 60 2.5 55 95 85 1.0 1.0 TYP 2 0.1 2 85 69 2.8 -0.5 73 105 95 2.6 1.7 MAX 10 10 15 0 4.0 4.0 MIN 75 60 2.5 60 100 90 1.0 1.0 CA5130A TYP 1.5 0.1 2 87 69 2.8 -0.5 75 105 97 3.1 1.4 MAX 4 5 10 0 4.0 4.0 UNITS mV pA pA dB dB V V dB dB dB mA mA
PARAMETER Input Offset Voltage Input Offset Current Input Current Common Mode Rejection Ratio
SYMBOL VIO IIO II CMRR
2
CA5130, CA5130A
Electrical Specifications TA = -55oC to 125oC, V+ = 5V, V- = 0V, Unless Otherwise Specified TEST CONDITIONS VO = 2.5V VO = 2.5V VO = 2.5V VCM = 0V to 1V VCM = 0V to 2.5V Input Common Mode Voltage Range Power Supply Rejection Ratio Large Signal Voltage Gain (Note 4) VICR+ VICRPSRR AOL + = 1V; - = 1V VO = 0.1V to 4.1V RL = VO = 0.1V to 3.6V RL = 10k Source Current Sink Current Output Voltage VOM+ VOMVOM+ VOMVOM+ VOMSupply Current ISUPPLY VO = 0V VO = 2.5V NOTE: 4. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10k. Electrical Specifications TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified TEST CONDITIONS V = 7.5V V = 7.5V V = 7.5V CA5130 MIN 70 10 VIO/V V = 7.5V VO = 10VP-P RL = 2k 50 94 TYP 8 0.5 5 90 -0.5 to 12 32 320 110 MAX 15 30 50 0 320 MIN 80 10 50 94 CA5130A TYP 2 0.5 5 90 -0.5 to 12 32 320 110 MAX 5 20 30 0 150 UNITS mV pA pA dB V V/V kV/V dB RL = 2k RL = 10k ISOURCE ISINK VOUT RL = 4.99 4.0 2.0 5 0 4.6 0 3.0 0 80 300 0.01 0.01 0.01 220 500 4.99 4.0 2.0 5 0 4.6 0 3.0 0 80 300 0.01 0.01 0.01 220 500 V V V V V V A A VO = 0V VO = 5V CA5130 MIN 60 50 2.5 40 90 75 0.6 0.6 TYP 3 0.1 2 80 80 2.8 -0.5 66 98 85 MAX 15 10 15 0 5.0 5.0 MIN 60 55 2.5 45 94 80 0.6 0.6 CA5130A TYP 2 0.1 2 80 80 2.8 -0.5 70 98 88 2.2 1.15 MAX 10 5 10 0 5.0 5.0 UNITS mV nA nA dB dB V V dB dB dB mA mA
PARAMETER Input Offset Voltage Input Offset Current Input Current Common Mode Rejection Ratio
SYMBOL VIO IIO II CMRR
PARAMETER Input Offset Voltage Input Offset Current Input Current Common Mode Rejection Ratio Input Common Mode Voltage Range Power Supply Rejection Ratio Large Signal Voltage Gain
SYMBOL VIO IIO II CMRR VICR PSRR AOL
3
CA5130, CA5130A
Electrical Specifications TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified (Continued) TEST CONDITIONS CA5130 MIN TYP MAX MIN CA5130A TYP MAX UNITS
PARAMETER Maximum Output Current Source Sink Supply Current
SYMBOL
IOM+ IOMISUPPLY
VO = 0V VO = 15V VO = 7.5V, RL = VO = 0V, RL =
12 12 -
22 20 10 2
45 45 15 3
12 12 -
22 20 10 2
45 45 15 3
mA mA mA mA
Maximum Output Voltage VOM+ VOMVOM+ VOMInput Offset Voltage Temperature Drift Electrical Specifications
VOUT
RL =
14.99 -
15 0 13.3 0.002 10
0.01 0.01 -
14.99 12 -
15 0 13.3 0.002 10
0.01 0.01 -
V V V V V/oC
RL = 2k
12 -
VIO/T
-
Typical Values Intended Only for Design Guidance, At TA = 25oC, VSUPPLY = 7.5V Unless Otherwise Specified CA5130 CA5130A TYP 22 1.5 4.3 23 15 4 UNITS mV T pF V MHz MHz
PARAMETER Input Offset Voltage Adjustment Range Input Resistance Input Capacitance Equivalent Input Noise Voltage Open Loop Crossover Frequency For Unity Gain Stability 47pF Required Slew Rate Open Loop Closed Loop Transient Response Rise Time Overshoot Settling Time (To <0.1%, VIN = 4VP-P) NOTE:
SYMBOL
TEST CONDITIONS 10k Across Terminals 4 and 5 or 4 and 1
TYP 22 1.5
RI CI eN fT f = 1MHz BW = 0.2MHz, RS = 1M (Note 5) CC = 0 CC = 47pF SR CC = 0 CC = 56pF tr OS tS CC = 56pF, CL = 25pF, RL = 2k (Voltage Follower) CC = 56pF, CL = 25pF, RL = 2k (Voltage Follower)
4.3 23 15 4
30 10
30 10
V/s V/s s % s
0.09 10 1.2
0.09 10 1.2
5. Although a 1M source is used for this test, the equivalent input noise remains constant for values of RS up to 10M.
4
CA5130, CA5130A Schematic Diagram
BIAS CIRCUIT CURRENT SOURCE FOR Q6 AND Q7 Q1 D1 Z1 8.3V R1 40k R 2 5k INPUT STAGE D5 D6 (NOTE 6) D7 D8 OUTPUT STAGE Q6 Q7 SECOND STAGE D2 D3 D4 Q4 Q5 Q2 "CURRENT SOURCE LOAD" FOR Q11 Q3 7 V+
NON-INV. INPUT + INV. INPUT 2 3
Q8 OUTPUT 6
R3 1k Q9 Q10 R4 1k Q11 Q12
R5 1k
R6 1k
5
OFFSET NULL
1
COMPENSATION
8
STROBING
4
V-
NOTE: 6. Diodes D5 through D8 provide gate oxide protection for MOSFET Input Stage.
Block Diagram
CA5130 200A 1.35mA 200A 8mA (NOTE 7) 0mA (NOTE 8) V+ 7
NOTES: 7. Total supply voltage (for indicated voltage gains) = 15V with input terminals biased so that Terminal 6 potential is +7.5V above Terminal 4. 8. Total supply voltage (for indicated voltage gains) = 15V with output terminal driven to either supply rail.
BIAS CKT.
+ 3 INPUT 2 AV 5X AV 6000X AV 30X OUTPUT 6
-
V4 CC 5 1 COMPENSATION (WHEN REQUIRED) 8 STROBE
OFFSET NULL
5
CA5130, CA5130A Application Information
Circuit Description
The input terminals shown in the block diagram of the CA5130 Series CMOS Operational Amplifiers may be operated down to 0.5V below the negative supply rail, and the output can be swung very close to either supply rail in many applications. Consequently, the CA5130 Series circuits are ideal for single supply operation. Three Class A amplifier stages, having the individual gain capability and current consumption shown in the Block Diagram, provide the total gain of the CA5130. A biasing circuit provides two potentials for common use in the first and second stages. Terminal 8 can be used both for phase compensation and to strobe the output stage into quiescence. When Terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output potential at Terminal 6 essentially rises to the positive supply rail potential at Terminal 7. This condition of essentially zero current drain in the output stage under the strobed "OFF" condition can only be achieved when the ohmic load resistance presented to the amplifier is very high (e.g., when the amplifier output is used to drive CMOS digital circuits in comparator applications). junction of resistor R1 and diode D4 provides a gate bias potential of about 4.5V for PMOS transistors Q4 and Q5 with respect to Terminal 7. A potential of about 2.2V is developed across diode connected PMOS transistor Q1 with respect to Terminal 7 to provide gate bias for PMOS transistors Q2 and Q3. It should be noted that Q1 is "mirror connected" to both Q2 and Q3. Since transistors Q1, Q2, Q3 are designed to be identical, the approximately 200A current in Q1 establishes a similar current in Q2 and Q3 as constant current sources for both the first and second amplifier stages, respectively. At total supply voltages somewhat less than 8.3V, zener diode Z1 becomes nonconductive and the potential, developed across series connected R1, D1-D4, and Q1, varies directly with variations in supply voltage. Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in accordance with supply voltage variations. This variation results in deterioration of the power supply rejection ratio (PSRR) at total supply voltages below 8.3V. Operation at total supply voltages below about 4.5V results in seriously degraded performance.
Output Stage
The output stage consists of a drain loaded inverting amplifier using CMOS transistors operating in the Class A mode. When operating into very high resistance load, the output can be swung within mV of either supply rail. Because the output stage is a drain loaded amplifier, its gain is dependent upon the load impedance. The transfer characteristics of the output stage for a load returned to the negative supply rail are shown in Figure 15. Typical op amp loads are readily driven by the output stage. Because large signal excursions are nonlinear, requiring feedback for good waveform reproduction, transient delays may be encountered. As a voltage follower, the amplifier can achieve 0.01% accuracy levels, including the negative supply rail.
Input Stages
The circuit of the CA5130 is shown in the Schematic Diagram. It consists of a differential input stage using PMOS field-effect transistors (Q6, Q7) working into a mirror pair of bipolar transistors (Q9, Q10) functioning as load resistors together with resistors R3 through R6. The mirror pair transistors also function as a differential-to-single-ended converter to provide base drive to the second stage bipolar transistor (Q11). Offset nulling, when desired, can be effected by connecting a 100,000 potentiometer across Terminals 1 and 5 and the potentiometer slider arm to Terminal 4. Cascode connected PMOS transistors Q2, Q4 are the constant current source for the input stage. The biasing circuit for the constant current source is subsequently described. The small diodes D5 through D8 provide gate oxide protection against high voltage transients, e.g., including static electricity during handling for Q6 and Q7.
Input Current Variation with Common Mode Input Voltage
As shown in the Table of Electrical Specifications, the input current for the CA5130 Series Op Amps is typically 5pA at TA = 25oC when Terminals 2 and 3 are at a common mode potential of +7.5V with respect to negative supply Terminal 4. Figure 24 contains data showing the variation of input current as a function of common mode input voltage at TA = 25oC. This data shows that circuit designers can advantageously exploit these characteristics to design circuits which typically require an input current of less than 1pA, provided the common mode input voltage does not exceed 2V. As previously noted, the input current is essentially the result of the leakage current through the gate protection diodes in the input circuit and, therefore, a function of the applied voltage. Although the finite resistance of the glass terminal-to-case insulator of the metal can package also contributes an increment of leakage current, there are useful compensating factors. Because the gate protection network functions as if it is connected to Terminal 4 potential, and the metal can case of the CA5130 is also internally tied to Terminal 4, input Terminal 3 is essentially "guarded" from spurious leakage currents.
Second Stage
Most of the voltage gain in the CA5130 is provided by the second amplifier stage, consisting of bipolar transistor Q11 and its cascode connected load resistance provided by PMOS transistors Q3 and Q5. The source of bias potentials for these PMOS transistors is subsequently described. Miller-Effect compensation (roll-off) is accomplished by simply connecting a small capacitor between Terminals 1 and 8. A 47pF capacitor provides sufficient compensation for stable unity gain operation in most applications.
Bias Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R2 and zener diode Z1 serve to establish a voltage of 8.3V across the series connected circuit, consisting of resistor R1, diodes D1 through D4, and PMOS transistor Q1. A tap at the 6
CA5130, CA5130A
Offset Nulling
Offset voltage nulling is usually accomplished with a 100,000 potentiometer connected across Terminals 1 and 5 and with the potentiometer slider arm connected to Terminal 4. A fine offset null adjustment usually can be effected with the slider arm positioned in the midpoint of the potentiometer's total range.
V+ 7 3 CA5130 + Q8 6 Q12 RL
Input Current Variation with Temperature
The input current of the CA5130 Series circuits is typically 5pA at 25oC. The major portion of this input current is due to leakage current through the gate protective diodes in the input circuit. As with any semiconductor junction device, including op amps with a junction FET input stage, the leakage current approximately doubles for every 10oC increase in temperature. Figure 25 provides data on the typical variation of input bias current as a function of temperature in the CA5130. In applications requiring the lowest practical input current and incremental increases in current because of "warm-up" effects, it is suggested that an appropriate heat sink be used with the CA5130. In addition, when "sinking" or "sourcing" significant output current the chip temperature increases, causing an increase in the input current. In such cases, heatsinking can also very markedly reduce and stabilize input current variations.
2
4 8
V-
FIGURE 1A. DUAL POWER SUPPLY OPERATION
V+ 7 3 CA5130 + Q8 6 2 Q12 RL
4 8
Input Offset Voltage (VIO) Variation with DC Bias vs Device Operating Life
It is well known that the characteristics of a MOS/FET device can change slightly when a DC gate source bias potential is applied to the device for extended time periods. The magnitude of the change is increased at high temperatures. Users of the CA5130 should be alert to the possible impacts of this effect if the application of the device involves extended operation at high temperatures with a significant differential DC bias voltage applied across Terminals 2 and 3. Figure 26 shows typical data pertinent to shifts in offset voltage encountered with CA5130 devices (metal can package) during life testing. At lower temperatures (metal can and plastic packages), for example at 85oC, this change in voltage is considerably less. In typical linear applications where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage. The 2V differential voltage example represents conditions when the amplifier output stage is "toggled", e.g., as in comparator applications.
FIGURE 1B. SINGLE POWER SUPPLY OPERATION FIGURE 1. CA5130 OUTPUT STAGE IN DUAL AND SINGLE POWER SUPPLY OPERATION
Dual supply operation: When the output voltage at Terminal 6 is 0V, the currents supplied by the two power supplies are equal. When the gate terminals of Q8 and Q12 are driven increasingly positive with respect to ground, current flow through Q12 (from the negative supply) to the load is increased and current flow through Q8 (from the positive supply) decreases correspondingly. When the gate terminals of Q8 and Q12 are driven increasingly negative with respect to ground, current flow through Q8 is increased and current flow through Q12 is decreased accordingly. Single supply operation: Initially, let it be assumed that the value of RL is very high (or disconnected), and that the input terminal bias (Terminals 2 and 3) is such that the output terminal (No. 6) voltage is at V+/2, i.e., the voltage drops across Q8 and Q12 are of equal magnitude. Figure 16 shows typical quiescent supply current vs supply voltage for the CA5130 operated under these conditions. Since the output stage is operating as a Class A amplifier, the supply current will remain constant under dynamic operating conditions as long as the transistors are operated in the linear portion of their voltage transfer characteristics (see Figure 15). If either Q8 or Q12 are swung out of their linear regions toward cutoff (a nonlinear region), there will be a corresponding reduction in supply current. In the extreme case, e.g., with Terminal 8 swung down to ground potential (or tied to ground), NMOS transistor Q12 is completely cut off and the supply current to series connected
Power-Supply Considerations
Because the CA5130 is very useful in single supply applications, it is pertinent to review some considerations relating to power supply current consumption under both single and dual supply service. Figures 1A and 1B show the CA5130 connected for both dual and single supply operation.
7
CA5130, CA5130A
transistors Q8, Q12 goes essentially to zero. The two preceding stages in the CA5130, however, continue to draw modest supply current (see the lower curve in Figure 16) even though the output stage is strobed off. Figure 1A shows a dual supply arrangement for the output stage that can also be strobed off, assuming RL = , by pulling the potential of Terminal 8 down to that of Terminal 4. Let it now be assumed that a load resistance of nominal value (e.g., 2k) is connected between Terminal 6 and ground in the circuit of Figure 1B. Let it further be assumed that the input terminal bias (Terminals 2 and 3) is such that the output terminal (No. 6) voltage is at V+/2. Since PMOS transistor Q8 must now supply quiescent current to both RL and transistor Q12, it should be apparent that under these conditions the supply current must increase as an inverse function of the RL magnitude. Figure 22 shows the voltage drop across PMOS transistor Q8 as a function of load current at several supply voltages. Figure 15 shows the voltage transfer characteristics of the output stage for several values of load resistance.
Typical Applications
Voltage Followers
Operational amplifiers with very high input resistances, like the CA5130, are particularly suited to service as voltage followers. Figure 3 shows the circuit of a classical voltage follower, together with pertinent waveforms using the CA5130 in a split supply configuration. A voltage follower, operated from a single supply, is shown in Figure 4, together with related waveforms. This follower circuit is linear over a wide dynamic range, as illustrated by the reproduction of the output waveform in Figure 4A with input signal ramping. The waveforms in Figure 4B show that the follower does not lose its input-to-output phase sense, even though the input is being swung 7.5V below ground potential. This unique characteristic is an important attribute in both operational amplifier and comparator applications. Figure 4B also shows the manner in which the CMOS output stage permits the output signal to swing down to the negative supply rail potential (i.e., ground in the case shown). The digital-toanalog converter (DAC) circuit, described in the following section, illustrates the practical use of the CA5130 in a single supply voltage follower application.
Wideband Noise
From the standpoint of low noise performance considerations, the use of the CA5130 is most advantageous in applications where the source resistance of the input signal is on the order of 1M or more. In this case, the total input referred noise voltage is typically only 23V when the test circuit amplifier of Figure 2 is operated at a total supply voltage of 15V. This value of total input referred noise remains essentially constant, even though the value of source resistance is raised by an order of magnitude. This characteristic is due to the fact that reactance of the input capacitance becomes a significant factor in shunting the source resistance. It should be noted, however, that for values of source resistance very much greater than 1M, the total noise voltage generated can be dominated by the thermal noise contributions of both the feedback and source resistors.
9-Bit CMOS DAC
A typical circuit of a 9-bit Digital-to-Analog Converter (DAC) (see Note) is shown in Figure 5. This system combines the concepts of multiple switch CMOS lCs, a low cost ladder network of discrete metal-oxide film resistors, a CA5130 op amp connected as a follower, and an inexpensive monolithic regulator in a simple single power supply arrangement. An additional feature of the DAC is that it is readily interfaced with CMOS input logic, e.g., 10V logic levels are used in the circuit of Figure 5.
NOTE: "Digital-to-Analog Conversion Using the Intersil CD4007A CMOS lC", Application Note AN6080.
+7.5V
Rs 3 1M 2 +
0.01F 7 6 NOISE VOLTAGE OUTPUT
4 8 1 0.01 F
30.1k
47pF -7.5V BW (-3dB) = 200kHz TOTAL NOISE VOLTAGE (REFERRED TO INPUT) = 23V (TYP) 1k
FIGURE 2. CA5130 OUTPUT STAGE IN DUAL AND SINGLE POWER SUPPLY OPERATION
8
CA5130, CA5130A
+7.5V
0.01F 7 3 10k 2 + 6
8 1
4
2k 0.01F
-7.5V CC = 56pF 2k BW (-3dB) = 4MHz SR = 10V/s 0.1F
25pF
Top Trace: Output Bottom Trace: Input FIGURE 3A. SMALL SIGNAL RESPONSE (50mV/DIV., 200ns/DIV.)
Top Trace: Output Signal = 2V/Div., 5s/Div. Center Trace: Difference Signal = 5mV/Div., 5s/Div. Bottom Trace: Input Signal = 2V/Div., 5s/Div. FIGURE 3B. INPUT OUTPUT DIFFERENCE SIGNAL SHOWING SETTLING TIME (MEASUREMENT MADE WITH TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER)
FIGURE 3. CA5130 SPLIT SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS
9
CA5130, CA5130A
+15V
7 3 10k 2 +
0.01F
6
4 1 8 5 100k OFFSET ADJUST 2k
56pF
0.1F
0V
0V
0V
2V/Div., 500s/Div.
Top Trace: Output = 5V/Div., 200s/Div. Bottom Trace: Input = 5V/Div., 200s/Div. FIGURE 4B. OUTPUT WAVEFORM WITH GROUND REFERENCE SINE WAVE INPUT
FIGURE 4A. OUTPUT WAVEFORM WITH INPUT SIGNAL RAMPING
FIGURE 4. SINGLE SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS. (e.g., FOR USE IN SINGLE SUPPLY D/A CONVERTER; SEE FIGURE 9 IN AN6080)
The circuit uses an R/2R voltage ladder network, with the output potential obtained directly by terminating the ladder arms at either the positive or the negative power supply terminal. Each CD4007A contains three "inverters", each "inverter" functioning as a single pole double throw switch to terminate an arm of the R/2R network at either the positive or negative power supply terminal. The resistor ladder is an assembly of one percent tolerance metal oxide film resistors. The five arms requiring the highest accuracy are assembled with series and parallel combinations of 806,000 resistors from the same manufacturing lot. A single 15V supply provides a positive bus for the CA5130 follower amplifier and feeds the CA3085 voltage regulator. A "scale adjust" function is provided by the regulator output control, set to a nominal 10V level in this system. The line voltage regulation (approximately 0.2%) permits a 9-bit accuracy to be maintained with variations of several volts in 10
the supply. The flexibility afforded by the CMOS building blocks simplifies the design of DAC systems tailored to particular needs.
Single Supply, Absolute Value, Ideal Full Wave Rectifier
The absolute value circuit using the CA5130 is shown in Figure 6. During positive excursions, the input signal is fed through the feedback network directly to the output. Simultaneously, the positive excursion of the input signal also drives the output terminal (No. 6) of the inverting amplifier in a negative going excursion such that the 1N914 diode effectively disconnects the amplifier from the signal path. During a negative going excursion of the input signal, the CA5130 functions as a normal inverting amplifier with a gain equal to -R2/R1. When the equality of the two equations shown in Figure 6 is satisfied, the full wave output is symmetrical.
CA5130, CA5130A
Peak Detectors
Peak detector circuits are easily implemented with the CA5130, as illustrated in Figure 7 for both the peak positive and the peak negative circuit. It should be noted that with large signal inputs, the bandwidth of the peak negative circuit is much less than that of the peak positive circuit. The second stage of the CA5130 limits the bandwidth in this case. Negative going output signal excursion requires a positive going signal excursion at the collector of transistor Q11, which is loaded by the intrinsic capacitance of the associated circuitry in this mode. On the other hand, during a negative going signal excursion at the collector of Q11, the transistor functions in active "pull down" mode so that the intrinsic capacitance can be discharged more expeditiously.
Function Generator
Figure 11 contains a schematic diagram of a function generator using the CA5130 in the integrator and threshold detector functions. This circuit generates a triangular or square wave output that can be swept over a 1,000,000:1 range (0.1Hz to 100kHz) by means of a single control, R1. A voltage control input is also available for remote sweep control. The heart of the frequency determining system is an operational transconductance amplifier (OTA) (see Note 9), lC1, operated as a voltage controlled current source. The output, IO, is a current applied directly to the integrating capacitor, C1, in the feedback loop of the integrator lC2, using a CA5130, to provide the triangular wave output. Potentiometer R2 is used to adjust the circuit for slope symmetry of positive going and negative going signal excursions. Another CA5130, lC3, is used as a controlled switch to set the excursion limits of the triangular output from the integrator circuit. Capacitor C2 is a "peaking adjustment" to optimize the high frequency square wave performance of the circuit. Potentiometer R3 is adjustable to perfect the "amplitude symmetry" of the square wave output signals. Output from the threshold detector is fed back via resistor R4 to the input of lC1 so as to toggle the current source from plus to minus in generating the linear triangular wave.
Error Amplifier In Regulated Power Supplies
The CA5130 is an ideal choice for error amplifier service in regulated power supplies since it can function as an error amplifier when the regulated output voltage is required to approach 0V. Figure 8 shows the schematic diagram of a 40mA power supply capable of providing regulated output voltage by continuous adjustment over the range from 0V to 13V. Q3 and Q4 in IC2 (a CA3066 transistor array lC) function as zeners to provide supply voltage for the CA5130 comparator (lC1). Q1, Q2, and Q5 in lC2 are configured as a low impedance, temperature compensated source of adjustable reference voltage for the error amplifier. Transistors Q1, Q2, Q3, and Q4 in lC3 (another CA3086 transistor array lC) are connected in parallel as the series pass element. Transistor Q5 in lC3 functions as a current limiting device by diverting base drive from the series pass transistors, in accordance with the adjustment of resistor R2. Figure 9 contains the schematic diagram of a regulated power supply capable of providing regulated output voltage by continuous adjustment over the range from 0.1V to 50V and currents up to 1A. The error amplifier (lC1) and circuitry associated with lC2 function as previously described, although the output of lC1 is boosted by a discrete transistor (Q4) to provide adequate base drive for the Darlington connected series pass transistors Q1, Q2. Transistor Q3 functions in the previously described current limiting circuit.
Operation with Output Stage Power-Booster
The current sourcing and sinking capability of the CA5130 output stage is easily supplemented to provide power boost capability. In the circuit of Figure 12, three CMOS transistor pairs in a single CA3600E (see Note 10) lC array are shown parallel connected with the output stage in the CA5130. In the Class A mode of CA3600E shown, a typical device consumes 20mA of supply current at 15V operation. This arrangement boosts the current handling capability of the CA5130 output stage by about 2.5X. The amplifier circuit in Figure 12 employs feedback to establish a closed-loop gain of 48dB. The typical large signal bandwidth (-3dB) is 50kHz.
NOTES: 9. See File No. 475 and AN6668. 10. See File No. 619 for technical information.
Multivibrators
The exceptionally high input resistance presented by the CA5130 is an attractive feature for multivibrator circuit design because it permits the use of timing circuits with high R/C ratios. The circuit diagram of a pulse generator (astable multivibrator), with provisions for independent control of the "on" and "off" periods, is shown in Figure 10. Resistors R1 and R2 are used to bias the CA5130 to the midpoint of the supply voltage and R3 is the feedback resistor. The pulse repetition rate is selected by positioning S1 to the desired position and the rate remains essentially constant when the resistors which determine "on period" and "off period" are adjusted.
11
CA5130, CA5130A
10V LOGIC INPUTS +10.010V LSB 9 6 14 11 2 CD4007A "SWITCHES" 9 13 7 8 4 806K 1% 5 402K 1% 200K 1% 1 12 8 100K 1% 806K 1% 5 13 1 12 806K 1% 806K 1% 750K 1% 806K 1% 13 8 (2) 806K 1% 1 12 5 (4) 806K 1% (8) 806K 1% CD4007A "SWITCHES" CD4007A "SWITCHES" MSB 1 10
8 3
7 10
6 6
5 3
4 10
3 6
2 3
BIT 1 2 3 4 5 6-9
REQUIRED RATIO-MATCH STANDARD 0.1% 0.2% 0.4% 0.8% 1% ABS
NOTE: All Resistances are In Ohms.
806K 1% VOLTAGE REGULATOR 1 2 CA3085 3 6 7 + 2F 25V 4 0.001F 8 22.1K 1% +10.010V
PARALLELED RESISTORS +15V 10K
+15V
62 OUTPUT 6 LOAD 4
7 + CA5130 3 VOLTAGE FOLLOWER 2
5 1 8
-
REGULATED VOLTAGE 1K ADJ. 3.83K 1%
100K OFFSET NULL 2K
56pF
0.1F
FIGURE 5. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA5130
R2 2k +15V 0.01 F 2 4k 3
R1
CA5130 + 5 1 8
7 6 4 1N914 5.1k R3 100k OFFSET ADJUST 0V
20pF
PEAK ADJUST 2k 0V
R2 R3 Gain = ------ = X = -------------------------------R1 R1 + R2 + R3 X + X2 R 3 = R 1 --------------- 1-X R2 2k ForX = 0.5: --------- = -----R1 4k 0.75 R 3 = 4k --------- = 6k 0.5
Top Trace: Output Signal = 2V/Div. Bottom Trace: Input Signal = 10V/Div. Time base on both traces = 0.2ms/Div.
20VP-P Input: BW (-3dB) = 230kHz, DC Output (Avg) = 3.2V 1VP-P Input: BW (-3dB) = 130kHz, DC Output (Avg) = 160mV FIGURE 6. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
12
CA5130, CA5130A
6VP-P INPUT; BW (-3dB) = 1.3MHz 0.3 VP-P INPUT; BW (-3dB) = 240kHz 3 10k 2 7 + CA5130 6 1N914 4 0.01F 2k -7.5V 2k -7.5V 100 k + +7.5V 0.01F +DC OUTPUT 10k 2 5F 0.01F 6VP-P INPUT; BW (-3dB) = 360kHz 0.3 VP-P INPUT; BW (-3dB) = 320kHz 3 7 + CA5130 6 1N914 4 100 k +7.5V 0.01F -DC OUTPUT
-
-
5F +
-
FIGURE 7A. PEAK POSITIVE DETECTOR CIRCUIT
FIGURE 7B. PEAK NEGATIVE DETECTOR CIRCUIT
FIGURE 7. PEAK-DETECTOR CIRCUITS
3
CURRENT LIMIT ADJ + R2 1k
IC3 CA3086 10 Q4 11 + 390 9 8 7 Q3 6 1 3
1k Q5 12 Q1 4 5 20k 1k 56pF 5F 25V 1 25F 7 6 8 ERROR AMPLIFIER 2 3 30k 100k VOLTAGE ADJUST OUTPUT 0 TO 13V AT 40mA + 13 14
Q2 2
0.01F
2.2k +
-
IC2 +20V INPUT CA3086 10 9 8, 7 6 6, 5 Q3 11 1, 2 Q4
Q1 3 Q2 4
CA5130 + 4
IC1 Q5 12 14 13 50k R1
62k
0.01F
NOTES: 11. Regulation (no load to full load): <0.01%. 12. Input Regulation: 0.02%/V. 13. Hum and noise output: <25V up to 100kHz. FIGURE 8. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)
-
13
CA5130, CA5130A
2N3055 + 2N2102 4.3k 1W 3.3k 1W 2N5294 + 1000pF 2.2k 1 IC2 CA3086 Q4 10, 11 1, 2 9 8, 7 3 5 Q1 6 Q5 12 14 13 Q4 5F + ERROR AMPLIFIER 3 10k 2 43k + 100F Q1 Q3 Q2 1 + 10k 1k CURRENT LIMIT ADJUST
+55V INPUT
100F
-
-
8 2N2102 7 + CA5130 IC1 4
OUTPUT: 0.1 TO 50V AT 1A
-
Q3 6 4
Q2
8.2k
1k 62k
50k VOLTAGE ADJUST
NOTES: 14. Regulation (no load to full load): <0.005%. 15. Input Regulation: 0.01%/V. 16. Hum and noise output: <250VRMS up to 100kHz. FIGURE 9. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A)
-
+15V
0.01F ON-PERIOD ADJUST 1M 2k R3 100k 7 3 1F R2 100k S1 + CA5130 2 6 OUTPUT 4 0.1F 0.01F 0.001F 2k OFF-PERIOD ADJUST 1M 2k
R1 100k
FREQUENCY RANGE: POSITION OF S1 0.001F 0.01F 0.1F 1F PULSE PERIOD 4s to 1ms 40s to 10ms 0.4ms to 100ms 4ms to 1s
-
FIGURE 10. PULSE GENERATOR (ASTABLE MULTIVIBRATOR) WITH PROVISIONS FOR INDEPENDENT CONTROL OF "ON" AND "OFF" PERIODS
14
CA5130, CA5130A
R4 270k VOLTAGE-CONTROLLED CURRENT SOURCE +7.5V IC1 3 3k 3k 2 +7.5V R2 100k + 7 CA3080A (NOTE) IO 6 2 3 -7.5V +7.5V SLOPE SYMMETRY 10k ADJUST VOLTAGE CONTROLLED INPUT R1 10k 1 -7.5V 56pF FREQUENCY ADJUST (100kHz MAX) -7.5V 1 R3 100k AMPLITUDE SYMMETRY ADJUST IC2 7 C2 6 39k 4 8 2 3 INTEGRATOR C1 100pF +7.5V HIGH - FREQ. ADJUST 3 - 30pF
THRESHOLD DETECTOR 150k +7.5V IC3 7 + CA5130 6 4 5
CA5130 +
4 5
-
10M
-7.5V
NOTE: See File Number 475 and AN6668 for technical information. FIGURE 11. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)
+15V
0.01F 1M 1F CA3600E (NOTE) 7 3 2k INPUT 1F 4 2 + CA5130 6 QP1
14
2
11
QP2
QP3
750k
13
1 500F
8 6 3 10 12
RL = 100 (PO = 150mW AT THD = 10%) 8 QN1 5 QN2 QN3
AV(CL) = 48dB LARGE SIGNAL BW (-3dB) = 50kHz
7 510k
4
9
NOTE: Transistors QP1, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the CA5130. See File Number 619. FIGURE 12. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA5130
15
CA5130, CA5130A Typical Performance Curves
120 AOL SUPPLY VOLTAGE: V+ = 15V; V- = 0V; TA = 25oC OPEN LOOP VOLTAGE GAIN (dB) 150 OPEN LOOP PHASE (DEGREES) LOAD RESISTANCE = 2k 140 130 120 110 100 90 80 -100
OPEN LOOP VOLTAGE GAIN (dB)
100 1 2 60 3
OL
4 3 2 -100
80
1
-200
40
4
-300
20
0 101
102
1: CL = 9pF, CC = 0pF, RL = 2: CL = 30pF, CC = 15pF, RL = 2k
103 104 105 106 FREQUENCY (Hz)
107
108
-50
3: CL = 30pF, CC = 47pF, RL = 2k 4: CL = 30pF, CC = 150pF, RL = 2k
0 50 TEMPERATURE (oC)
100
FIGURE 13. OPEN LOOP VOLTAGE GAIN AND PHASE SHIFT vs FREQUENCY
17.5 QUIESCENT SUPPLY CURRENT (mA) 15.0 OUTPUT VOLTAGE (V) 12.5 1k 10.0 7.5 5.0 2.5 500 SUPPLY VOLTAGE: V+ = 15V, V- = 0V TA = 25oC RL = 5k 2k
FIGURE 14. OPEN LOOP GAIN vs TEMPERATURE
15 12.5 10 7.5 5 2.5 0 0 2.5 5 7.5 10 12.5 15 17.5 20 GATE VOLTAGE, TERMINALS 4 AND 8 (V) 22.5
LOAD RESISTANCE = TA = 25oC, V- = 0V
OUTPUT VOLTAGE BALANCED = V+/2
OUTPUT VOLTAGE HIGH = V+ OR LOW = V-
6
8 10 12 14 16 TOTAL SUPPLY VOLTAGE (V)
18
FIGURE 15. VOLTAGE TRANSFER CHARACTERISTICS OF CMOS OUTPUT STAGE
14 QUIESCENT SUPPLY CURRENT (mA) 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 TOTAL SUPPLY VOLTAGE (V) 16 OUTPUT VOLTAGE = V+/2 V- = 0V TA = -55oC
FIGURE 16. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
600 V+ = 5V, V- = 0V 525 SUPPLY CURRENT (A) 450 375 300 225 150 75 0 0 0.5 1 1.5 2 2.5 3 3.5 OUTPUT VOLTAGE (V) 4 4.5 5 -55oC 125oC 25oC
25oC 125oC
FIGURE 17. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 18. SUPPLY CURRENT vs OUTPUT VOLTAGE
16
CA5130, CA5130A Typical Performance Curves
8 V+ = 5V, V- = 0V OUTPUT VOLTAGE SWING (V) 7 OUTPUT VOLTAGE SWING (V) 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 LOAD RESISTANCE (k) 9 10 11 -55oC 25oC 125oC
(Continued)
9 V+ = 5V, V- = 0V 8 7 6 5 4 3 2 1 0 0.1 0.2 0.6 1 2 4 68 20 40 80 LOAD RESISTANCE (k) 200 1000
FIGURE 19. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
FIGURE 20. OUTPUT SWING vs LOAD RESISTANCE
8 V+ = 5V, V- = 0V VOLTAGE DROP ACROSS PMOS OUTPUT TRANSISTOR (Q8) (V) 7 OUTPUT CURRENT (mA) 6 5 4 SINK 3 2 1 0 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (oC) SOURCE
50 10
V- = 0V TA = 25oC
V+ = 15V V+ = 10V V+ = 5V
1
0.1
0.01
0.001 0.001
0.01
0.1
1
10
100
MAGNITUDE OF LOAD CURRENT (mA)
FIGURE 21. OUTPUT CURRENT vs TEMPERATURE
FIGURE 22. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR (Q8) vs LOAD CURRENT
50 VOLTAGE DROP ACROSS PMOS OUTPUT TRANSISTOR (Q12) (V) 10 V- = 0V TA = 25oC V+ = 15V V+ = 10V V+ = 5V
10.0
TA = 25oC
INPUT VOLTAGE (V)
7.5 V+ 15V TO 5V 5.0 PA 3 2.5 VIN 8 4 0V TO -10V V0 7 2 CA5130 6
1
0.1
0.01
0.001 0.001
0.01 0.1 1 10 MAGNITUDE OF LOAD CURRENT (mA)
100
-1
0
1
2
3 4 5 6 INPUT CURRENT (pA)
7
FIGURE 23. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR (Q12) vs LOAD CURRENT
FIGURE 24. INPUT CURRENT vs COMMON MODE VOLTAGE
17
CA5130, CA5130A Typical Performance Curves
4000 VS = 7.5V OFFSET VOLTAGE SHIFT (mV)
(Continued)
7 6 5 4 3 2 1 0 DIFFERENTIAL DC VOLTAGE (ACROSS TERMS. 2 AND 3) = 0V OUTPUT VOLTAGE = V+ / 2 DIFFERENTIAL DC VOLTAGE (ACROSS TERMINALS 2 AND 3) = 2V OUTPUT STAGE TOGGLED TA = 125oC FOR METAL CAN PACKAGE
1000 INPUT CURRENT (pA)
100
10
1 -80
-60
-40
-20
0 20 40 60 80 TEMPERATURE (oC)
100 120 140
0
500
1000
1500
2000 2500 3000 TIME (HOURS)
3500
4000
FIGURE 25. INPUT CURRENT vs TEMPERATURE
FIGURE 26. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT vs OPERATING LIFE
18
CA5130, CA5130A Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 8
2.93
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
19

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